Method and apparatus for dark current and hot pixel reduction in active pixel image sensors

ABSTRACT

A method of operating an imager pixel that includes the act of applying a relatively small voltage on the gate of a transfer transistor during a charge acquisition period. If a small positive voltage is applied, a depletion region is created under the transfer transistor gate, which creates a path for dark current electrons to be transferred to a pixel floating diffusion region. The dark electrons are subsequently removed by a pixel reset operation. If a small negative voltage is applied to the transfer gate, electrons that would normally create dark current problems will instead recombine with holes thereby substantially reducing dark current.

FIELD OF THE INVENTION

The invention relates generally to imaging devices and more particularlyto dark current and hot pixel reduction in active pixel image sensors.

BACKGROUND

A CMOS imager circuit includes a focal plane array of pixel cells, eachone of the cells including a photosensor, for example, a photogate,photoconductor or a photodiode for accumulating photo-generated chargein the specified portion of the substrate. Each pixel cell has a chargestorage region, formed on or in the substrate, which is connected to thegate of an output transistor that is part of a readout circuit. Thecharge storage region may be constructed as a floating diffusion region.In some imager circuits, each pixel may include at least one electronicdevice such as a transistor for transferring charge from the photosensorto the storage region and one device, also typically a transistor, forresetting the storage region to a predetermined charge level prior tocharge transference.

In a CMOS imager, the active elements of a pixel cell perform thefunctions of: (1) photon to charge conversion; (2) accumulation of imagecharge; (3) resetting the storage region to a known state before thetransfer of charge to it; (4) transfer of charge to the storage region;(5) selection of a pixel for readout; and (6) output and amplificationof a signal representing pixel charge. Photo charge may be amplifiedwhen it moves from the initial charge accumulation region to the storageregion. The charge at the storage region is typically converted to apixel output voltage by a source follower output transistor.

CMOS imagers of the type discussed above are generally known asdiscussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No.6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat.No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to MicronTechnology, Inc., which are hereby incorporated by reference in theirentirety.

A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1.The pixel 10 includes a photosensor 12, implemented as a pinnedphotodiode, transfer transistor 14, floating diffusion region FD, resettransistor 16, source follower transistor 18 and row select transistor20. The photosensor 12 is connected to the floating diffusion region FDby the transfer transistor 14 when the transfer transistor 14 isactivated by a transfer gate control signal TX.

The reset transistor 16 is connected between the floating diffusionregion FD and a pixel supply voltage Vpix. A reset control signal RST isused to activate the reset transistor 16, which resets the floatingdiffusion region FD to the pixel supply voltage Vpix level as is knownin the art.

The source follower transistor 18 has its gate connected to the floatingdiffusion region FD and is connected between an array supply voltage Vaaand the row select transistor 20. The source follower transistor 18converts the charge stored at the floating diffusion region FD into anelectrical output voltage signal PIX OUT. The row select transistor 20is controllable by a row select signal SEL for selectively connectingthe source follower transistor 18 and its output voltage signal PIX OUTto a column line 22 of a pixel array.

FIG. 1 b illustrates a typical timing diagram for the readout andphoto-charge acquisition operations for the pixel 10 illustrated in FIG.1 a. FIG. 1 b illustrates a first readout period 30 in which previouslystored photo-charges are readout of the pixel 10. During this firstreadout period 30, the reset control signal RST is pulsed to activatethe reset transistor 16, which resets the floating diffusion region FDto the pixel supply voltage Vpix level. While the SEL signal is high, asample and hold reset signal SHR is pulsed to store a reset signal Vrst(corresponding to the reset floating diffusion region FD) on a sampleand hold capacitor. The transfer control signal TX is then activated toallow photo-charges from the photosensor 12 to be transferred to thefloating diffusion region FD. While the SEL signal remains high, asample and hold pixel signal SHS is pulsed to store a pixel signal Vsigfrom the pixel 10 on another sample and hold capacitor.

During the acquisition period 32, the reset control signal RST, transfercontrol signal TX and sample and hold signals SHR, SHS are set to aground potential GRND. It is during the acquisition period 32 that thephotosensor 12 accumulates photo-charge based on the light incident onthe photosensor 12. After the acquisition period 32, a second readoutperiod 34 begins. During the second readout period 34, the photo-chargesaccumulated in the acquisition period 32 are readout of the pixel 10 (asdescribed above for period 30).

One common problem associated with conventional imager pixel cells, suchas pixel cell 10, is dark current (that is, current generated as aphotodiode signal in the absence of light). As shown in the potentialdiagram of FIG. 1 c, a major component of dark current occurs underneaththe gate of the transfer transistor 14. These “dark carriers” 25 areaccumulated on the pinned photodiode photosensor 12 during integration(i.e., during the acquisition period 32), which creates parasitic darkcharge that is added to the light signals when they are readout. This isundesirable.

Accordingly, there is a desire and need to reduce dark current and thefactors that cause dark current in imagers.

SUMMARY

The invention provides a method of operating an imager pixel such thatdark current and the factors that cause dark current in imagers arereduced.

The above and other features and advantages are achieved in variousexemplary embodiments of the invention by a method of operating animager pixel that includes the act of applying a relatively smallvoltage on the gate of a transfer transistor during a charge acquisitionperiod. If a small positive voltage is applied, a depletion region iscreated under the transfer transistor gate, which creates a path fordark current electrons to be transferred to a pixel floating diffusionregion. The dark electrons are subsequently removed by a pixel resetoperation. If a small negative voltage is applied to the transfer gate,electrons that would normally create dark current problems will insteadrecombine with holes thereby substantially reducing dark current.

In other aspects of the invention, the application of the small positiveor negative voltage is dependent upon the imager's gain settings beingused at that time. By monitoring the gain of the imager, which isindicative of the light intensity on the imager pixels, the smallpositive or negative voltage will be applied to the gate of the transfertransistor under high gain (or dark) conditions only. For low gain (orbright light) conditions, a ground potential or zero voltage is appliedto the gate of the transfer transistor. For embodiments using a smallpositive voltage, this provides maximum hot pixel reduction for the highgain conditions, while allowing maximum full well capacity for the lowgain conditions. For embodiments using a small negative voltage, thisprovides maximum electron recombination for the high gain conditions,while avoiding blooming issues during the low gain conditions.

In yet another aspect of the invention, the voltage applied to thetransfer gate is scaled according to the gain setting of the imager atthe time. That is, a range of different voltages (both negative andpositive) may be applied to the gate of the transfer transistor based ona range of gain settings between the high and low gain settings,providing dark current and hot pixel reduction at high gain, preservingfull well capacity at low gain, and allowing anti-blooming protection atsaturated conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

FIG. 1 a illustrates a conventional imager pixel circuit;

FIG. 1 b illustrates a timing diagram for operating the pixel circuit ofFIG. 1 a in a conventional manner;

FIG. 1 c illustrates a voltage potential diagram for the pixel circuitof FIG. 1 a when operated in accordance with the FIG. 1 b timingdiagram;

FIG. 2 a illustrates a timing diagram for operating the pixel circuit ofFIG. 1 a in accordance with an exemplary embodiment of the invention;

FIG. 2 b illustrates a voltage potential diagram for the pixel circuitof FIG. 1 a when operated in accordance with the FIG. 2 a timingdiagram;

FIG. 2 c illustrates another voltage potential diagram for the pixelcircuit of FIG. 1 a when operated in accordance with the invention;

FIG. 3 a illustrates a timing diagram for operating the pixel circuit ofFIG. 1 a in accordance with another exemplary embodiment of theinvention;

FIG. 3 b illustrates a voltage potential diagram for the pixel circuitof FIG. 1 a when operated in accordance with the FIG. 3 a timingdiagram;

FIGS. 4 a-4 f are histograms illustrating how the invention reduced darkcurrent in a first experiment using pixels having a first size;

FIGS. 5 a-5 f are histograms illustrating how the invention reduced darkcurrent in a second experiment using pixels having a second size;

FIGS. 6 a-6 f are histograms illustrating how the invention reduced darkcurrent in a third experiment using pixels having a third size;

FIG. 7 is a flowchart illustrating the processing of another embodimentof the invention.

FIG. 8 a shows an exemplary relationship of the small positive voltageand an imager's gain setting in accordance with the FIG. 7 embodiment ofthe invention;

FIG. 8 b shows an exemplary relationship of the small negative voltageand an imager's gain setting in accordance with the FIG. 7 embodiment ofthe invention;

FIG. 9 shows an imager constructed in accordance with an embodiment ofthe invention; and

FIG. 10 shows a processor system incorporating at least one imagerconstructed in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

The inventors have determined that the accumulation of dark charges 25(FIG. 1 c) from dark current generated underneath the transfertransistor 14 (FIG. 1 a) can be substantially reduced by applying arelatively small voltage to the gate of the transfer transistor 14during the charge acquisition cycle (also known as an integrationperiod). In a first exemplary embodiment of the invention, the smallvoltage is a relatively small positive voltage (e.g., within a range ofgreater than 0V to approximately 0.8V). In a second exemplary embodimentof the invention, the small voltage is a relatively small negativevoltage (e.g., within a range of less than 0V to approximately −0.6V).

FIG. 2 a illustrates a timing diagram for operating a pixel circuit suchas the pixel circuit 10 of FIG. 1 a in accordance with a first exemplaryembodiment of the invention. FIGS. 2 b and 2 c illustrate voltagepotential diagrams for the pixel circuit 10 (FIG. 1 a) when operated inaccordance with the FIG. 2 a timing diagram.

FIG. 2 a illustrates two readout periods 130, 134 and an acquisitionperiod 132. The two readout periods 130, 134 are the same as theconventional readout periods 30, 34 discussed above with reference toFIG. 1 b. That is, during this first readout period 130, for example,the reset control signal RST is pulsed to activate the reset transistor16 (FIG. 1 c), which resets the floating diffusion region FD to thepixel supply voltage Vpix level. While the SEL signal is high, a sampleand hold reset signal SHR is pulsed to store a reset signal Vrst(corresponding to the reset floating diffusion region FD) on a sampleand hold capacitor. The transfer control signal TX is activated to allowphoto-charges from the photosensor 12 to be transferred to the floatingdiffusion region FD. While the SEL signal is still high, a sample andhold pixel signal SHS is pulsed to store a pixel signal Vsig from thepixel on another sample and hold capacitor.

Dark electrons 125 are generated underneath the gate of the transfertransistor 14 in the region next to the pinned photodiode photosensor12. The dark electrons 125 may result from the surface states or bulksubstrate in that area. The inventors have determined that theaccumulation of the dark charges 125 can be substantially reduced byapplying a relatively small positive voltage to the gate of the transfertransistor 14 during the acquisition cycle 132. As is shown in thepotential diagram of FIG. 2 b, the application of the slightly positivevoltage on the gate of the transfer transistor 14 (FIG. 1 a) creates adepletion region 127 underneath the transfer transistor (TX ) gate. Thedepletion region 127 serves as a path for the dark electrons 125 toreach the floating diffusion region FD. Due to the difference inpotentials between the photodiode photosensor 12 and the floatingdiffusion region FD, the dark carriers 125 flow to the floatingdiffusion region FD and are drained away during a subsequent resetoperation instead of being captured by the photosensor 12 (as shown inFIG. 1 c). The remainder of the acquisition cycle 132 is substantiallythe same as the conventional acquisition cycle 32 discussed above withreference to FIG. 1 b.

The value of the small positive voltage depends on the threshold voltageof the transfer transistor 14, but a desired range for the voltage isfrom slightly greater than 0V to a voltage greater than a thresholdvoltage of the transfer transistor 14. For a regular CMOS-imagerprocess, the upper limit of the voltage range corresponds toapproximately 0.7-0.8 V. The maximum positive voltage could be limitedby ESD (electro static discharge) circuits in the real CMOS-imagerdesign. In this and all other examples, the voltage on the gate of thetransfer transistor 14 is referenced to the substrate voltage. FIG. 2 c.illustrates how different voltages VTX effect the depletion regionunderneath the transfer transistor 14 gate. That is, when the voltageVTX is set to 0V, the region underneath the transfer transistor issimilar to the region depicted in FIG. 1 c for the conventional pixeloperation. When the voltage VTX is set to 0.3V, there is a depletionregion 127 having a first slope underneath the transfer transistor 14.When the voltage VTX is set to 0.5V, there is a depletion region 127′having a second slope underneath the transfer transistor 14. The mannerin which different positive transfer gate voltages VTX effect thereduction of dark current is described below with reference to FIGS. 4a-6 f.

FIG. 3 a illustrates a timing diagram for operating a pixel circuit,such as the pixel circuit 10 illustrated in FIG. 1 a, in accordance withanother exemplary embodiment of the invention. FIG. 3 b illustrates avoltage potential diagram for the pixel circuit when operated inaccordance with the FIG. 3 a timing diagram. In the illustratedembodiment of the invention, a small negative voltage is applied to thegate of the transfer transistor 14 during the acquisition period 232(described below in more detail).

FIG. 3 a illustrates two readout periods 230, 234 and an acquisitionperiod 232. The two readout periods 230, 234 are the same as theconventional readout periods 30, 34 discussed above with reference toFIG. 1 b. That is, during this first readout period 230, for example,the reset control signal RST is pulsed to activate the reset transistor16 (FIG. 1 c), which resets the floating diffusion region FD to thepixel supply voltage Vpix level. A sample and hold reset signal SHR ispulsed to store a reset signal Vrst (corresponding to the reset floatingdiffusion region FD) on a sample and hold capacitor. The transfercontrol signal TX is activated to allow photo-charges from thephotosensor 12 to be transferred to the floating diffusion region FD. Asample and hold pixel signal SHS is pulsed to store a pixel signal Vsigfrom the pixel on another sample and hold capacitor.

Dark electrons (not shown) are generated underneath the gate of thetransfer transistor 14 in the region next to the pinned photodiodephotosensor 12. The inventors have determined that by applying arelatively small negative voltage to the gate of the transfer transistor14 during the acquisition period 232, the concentration of holes in theregion underneath the transfer transistor gate increases. When thishappens, dark electrons generated from the surface states under thetransfer transistor gate and/or from the bulk substrate of the pixelquickly recombine, leaving only a relatively small probability that theelectrons will get captured by the photosensor 12. Thus, dark currentand the factors that cause dark current are substantially reduced. FIG.3 b illustrates the case where all electrons are recombined (i.e., nodark electrons are shown).

The value of the small negative voltage depends on the threshold voltageof the transfer transistor 14, but a desired range for the voltage isfrom slightly less than 0V to a negative voltage with an absolute valuehigher than the absolute value of the threshold voltage of the transfertransistor 14. For a regular CMOS-imager process, the lower limit of thevoltage range corresponds to (−0.7)-(−0.8) V. The minimum negativevoltage could be limited by ESD circuits in the real CMOS-imager design.The manner in which different negative transfer gate voltages effect thereduction of dark current is described below with reference to FIGS. 4a-6 f.

FIGS. 4 a-4 f are histograms illustrating how the invention reduced darkcurrent in a first experiment using a test pixel array having 5.2 μmpixels. FIG. 4 a is a histogram showing dark current across the testpixel array when no voltage and small positive voltages are applied tothe transfer transistor gate. Curve 300 represents the dark current whenno voltage is applied to the transfer transistor gate. Curves 302, 304,306, 308, 310 represent the dark current when 0.1, 0.2, 0.3, 0.4, 0.5volts, respectively, are applied to the transfer transistor gate. FIG. 4b is a histogram showing cumulative dark current across the test pixelarray when no voltage and small positive voltages are applied to thetransfer transistor gate. Curve 320 represents the cumulative darkcurrent when no voltage is applied to the transfer transistor gate.Curves 322, 324, 326, 328, 330 represent the cumulative dark currentwhen 0.1, 0.2, 0.3, 0.4, 0.5 volts, respectively, are applied to thetransfer transistor gate.

FIG. 4 c is a histogram showing dark current across the test pixel arraywhen no voltage and small negative voltages are applied to the transfertransistor gate. Curve 340 represents the dark current when no voltageis applied to the transfer transistor gate. Curves 342, 344, 346, 350represent the dark current when −0.1, −0.2, −0.3, −0.5 volts,respectively, are applied to the transfer transistor gate. FIG. 4 d is ahistogram showing cumulative dark current across the test pixel arraywhen no voltage and small negative voltages are applied to the transfertransistor gate. Curve 360 represents the cumulative dark current whenno voltage is applied to the transfer transistor gate. Curves 362, 364,366, 370 represent the cumulative dark current when −0.1, −0.2, −0.3,−0.5 volts, respectively, are applied to the transfer transistor gate.

FIG. 4 e illustrates the average dark current for the experimental arrayhaving 5.2 μm pixels while FIG. 4 f illustrates the percentage ofaverage dark current for the experimental array. As shown in the graphs,the percentage of dark current is dramatically reduced when either thesmall positive voltage or small negative voltage are applied to thetransfer gates of the test pixel array during the acquisition period.

FIGS. 5 a-5 f are histograms illustrating how the invention reduced darkcurrent in a second experiment using a test pixel array having 4.2 μmpixels. FIG. 5 a is a histogram showing dark current across the testpixel array when no voltage and small positive voltages are applied tothe transfer transistor gate. Curve 400 represents the dark current whenno voltage is applied to the transfer transistor gate. Curves 402, 404,406, 408, 410 represent the dark current when 0.1, 0.2, 0.3, 0.4, 0.5volts, respectively, are applied to the transfer transistor gate. FIG. 5b is a histogram showing cumulative dark current across the test pixelarray when no voltage and small positive voltages are applied to thetransfer transistor gate. Curve 420 represents the cumulative darkcurrent when no voltage is applied to the transfer transistor gate.Curves 422, 424, 426, 428, 430 represent the cumulative dark currentwhen 0.1, 0.2, 0.3, 0.4, 0.5 volts, respectively, are applied to thetransfer transistor gate.

FIG. 5 c is a histogram showing dark current across the test pixel arraywhen no voltage and small negative voltages are applied to the transfertransistor gate. Curve 440 represents the dark current when no voltageis applied to the transfer transistor gate. Curves 442, 444, 446, 448,450 represent the dark current when −0.1, −0.2, −0.3, −0.4, −0.5 volts,respectively, are applied to the transfer transistor gate. FIG. 5 d is ahistogram showing cumulative dark current across the test pixel arraywhen no voltage and small negative voltages are applied to the transfertransistor gate. Curve 460 represents the cumulative dark current whenno voltage is applied to the transfer transistor gate. Curves 462, 464,466, 468, 470 represent the cumulative dark current when −0.1, −0.2,−0.3, −0.4, −0.5 volts, respectively, are applied to the transfertransistor gate.

FIG. 5 e illustrates the average dark current for the experimental arrayhaving 4.2 μm pixels while FIG. 5 f illustrates the percentage ofaverage dark current for the experimental array. As shown in the graphs,the percentage of dark current is dramatically reduced when either thesmall positive voltage or small negative voltage are applied to thetransfer gates of the test pixel array during the acquisition period.

FIGS. 6 a-6 f are histograms illustrating how the invention reduced darkcurrent in a third experiment using a test pixel array having 3.2 μmpixels. FIG. 6 a is a histogram showing dark current across the testpixel array when no voltage and small positive voltages are applied tothe transfer transistor gate. Curve 500 represents the dark current whenno voltage is applied to the transfer transistor gate. Curves 502, 504,506, 508, 510 represent the dark current when 0.1, 0.2, 0.3, 0.4, 0.5volts, respectively, are applied to the transfer transistor gate. FIG. 6b is a histogram showing cumulative dark current across the test pixelarray when no voltage and small positive voltages are applied to thetransfer transistor gate. Curve 520 represents the cumulative darkcurrent when no voltage is applied to the transfer transistor gate.Curves 522, 524, 526, 528, 530 represent the cumulative dark currentwhen 0.1, 0.2, 0.3, 0.4, 0.5 volts, respectively, are applied to thetransfer transistor gate.

FIG. 6 c is a histogram showing dark current across the test pixel arraywhen no voltage and small negative voltages are applied to the transfertransistor gate. Curve 540 represents the dark current when no voltageis applied to the transfer transistor gate. Curves 542, 544, 548, 550represent the dark current when −0.1, −0.2, −0.4, −0.5 volts,respectively, are applied to the transfer transistor gate. FIG. 6 d is ahistogram showing cumulative dark current across the test pixel arraywhen no voltage and small negative voltages are applied to the transfertransistor gate. Curve 560 represents the cumulative dark current whenno voltage is applied to the transfer transistor gate. Curves 562, 564,568, 570 represent the cumulative dark current when −0.1, −0.2, −0.4,−0.5 volts, respectively, are applied to the transfer transistor gate.

FIG. 6 e illustrates the average dark current for the experimental arrayhaving 3.2 μm pixels while FIG. 6 f illustrates the percentage ofaverage dark current for the experimental array. As shown in the graphs,the percentage of dark current is dramatically reduced when either thesmall positive voltage or small negative voltage are applied to thetransfer gates of the test pixel array during the acquisition period.

As can be seen from FIGS. 4 a-6 f, the inventions use of small positiveor negative voltage on the transfer transistor gate during chargeintegration greatly reduces the average dark current value and quantityof hot pixels.

The inventors have determined that it may not be desirable to apply thesmall voltage VTX to the gate of the transfer transistor under alllighting conditions. For example, applying the small voltage VTX to thegate of the transfer transistor may result in an associated drop in thephotosensor's full well capacity (and possibly lower its signal-to-noiseratio). This may not be desirable when the light intensity on the pixelis high. As another example, when the light intensity on the pixel ishigh and a small negative voltage VTX is applied to the gate of thetransfer transistor, there may be some blooming, which preferably shouldbe avoided.

FIG. 7 illustrates a method 600 designed to tie the small voltage VTXapplied to the gate of the transfer transistor during the acquisitionperiod to the light intensity or gain setting of the imager to preventany of the aforementioned undesirable effects from occurring. In normalimager operation, light intensity is monitored and an imager gainsetting is set based on the monitored light intensity. For example, whenthe light intensity is low, indicating a dark condition, the imager'sgain setting is usually set to a high value. Likewise, when the lightintensity is high, indicating a bright condition, the imager's gainsetting is usually set to a low value. The method 600 uses the imager'sgain setting to determine what the voltage VTX being applied to thetransfer transistor gate during the acquisition period should be.

Generally, it is desirable that the small positive or negative voltagebe applied to the gate of the transfer transistor under high gain (ordark) conditions only. For low gain (or bright light) conditions, aground potential or zero voltage is applied to the gate of the transfertransistor. For embodiments using a small positive voltage, thisprovides maximum hot pixel reduction for the high gain (dark)conditions, while allowing maximum full well capacity for the low gain(bright) conditions. For embodiments using a small negative voltage,this provides maximum electron recombination for the high gain (dark)conditions, while avoiding blooming issues during the low gain (bright)conditions.

The method 600 begins by determining the current gain setting for theimager (step 602). As set forth above, when the light intensity is low,indicating a dark condition, the imager's gain setting is usually set toa high value. When the light intensity is high, indicating a brightcondition, the imager's gain setting is usually set to a low value. Oncethe gain setting is determined, the level of the voltage VTX to beapplied to the transfer transistor gate during the acquisition period isdetermined (step 604). For example, when the gain setting is high, thetransfer gate voltage VIX is set to a non-zero positive or negativevoltage (as described above with respect to FIGS. 2 a, 3 a). When thegain setting is low, however, the transfer gate voltage VTX is set to azero voltage (as described above with respect to FIG. 1 b).

The values of the small voltage VTX can be pre-stored in a look-up tableor hardware register depending upon how the method 600 is implemented.In one embodiment, the method 600 is implemented by an image processoror a control circuit of the imager (described below with respect to FIG.9). In another embodiment, the voltage level can be determined by a userof the imager based on a measured gain setting. The user could use aninterface, such as a serial interface, to set a register within theimager, which will set the voltage VTX to the desired value. Thus, theinvention should not be limited to the exact technique used to implementthe method 600.

Once the level of the voltage VTX to be applied to the transfertransistor gate is determined (step 604), the voltage VTX is applied tothe gate of the transfer transistor during the acquisition period asdescribed above with respect to FIGS. 2 a and 3 a. Method 600 may simplyuse one voltage level when the gain setting is above a predefinethreshold and the zero voltage when the gain setting is below thepredefine threshold.

Often times, however, there are intermediate gain settings between thehigh gain and low gain settings. The method 600 may use differentvoltages VTX for each different gain setting used in the imager. Assuch, the voltage VTX applied to the transfer gate is scaled accordingto the gain setting of the imager at that time. Thus, in anotherembodiment of the invention, step 604 would set the level of thetransfer gate voltage VTX to one of a range of voltages based on aparticular gain setting or range of gain settings as desired.

The following examples will help illustrate the above embodiments of theinvention. In a first example, the exemplary voltages on the gate of thetransfer transistor and associated gain conditions provide dark currentand hot pixel reduction, and preserves maximum full well capacity: VTX=0at gain range from 1 to 2, VTX=0.2 V at gain>2, VTX=0.4 V at gain>3, andVTX=0.6 V at gain>4. In a second example, the exemplary voltages andassociated gain settings provide dark current and hot pixel reduction,while also allowing anti-blooming protection, and preserving full wellcapacity: VTX=0.05 V at gain range from 1 to 2, VTX=0.2 V at gain>2,VTX=0.4 V at gain>3, and VTX=0.6 V at gain>4. In a third example, theexemplary voltages and gain settings provide dark current and hot pixelreduction, while allowing anti-blooming protection and preserving fullwell capacity: VTX=0.05 V at gain range from 1 to 2, and VTX=−0.4 V atgain>2.

FIG. 8 a shows an exemplary relationship between the small positivevoltage VTX and an imager's gain setting and FIG. 8 b shows an exemplaryrelationship between the small negative voltage VTX and the imager'sgain setting in accordance with the invention. As such, any transfergate voltage VTX or range of transfer gate voltages, based on theassociated applicable gain setting or range of setting, can be used topractice the invention.

FIG. 9 illustrates an exemplary imager 700 that may utilize anyembodiment of the invention. The Imager 700 has a pixel array 705comprising pixels constructed as described above with respect to FIG. 1a, or using other pixel architectures. Row lines are selectivelyactivated by a row driver 710 in response to row address decoder 720. Acolumn driver 760 and column address decoder 770 are also included inthe imager 700. The imager 700 is operated by the timing and controlcircuit 750, which controls the address decoders 720, 770. The controlcircuit 750 also controls the row and column driver circuitry 710, 760in accordance with an embodiment of the invention (i.e., FIG. 2 a, FIG.3 a, FIG. 7).

A sample and hold circuit 761 associated with the column driver 760reads a pixel reset signal Vrst and a pixel image signal Vsig forselected pixels. A differential signal (Vrst-Vsig) is amplified bydifferential amplifier 762 for each pixel and is digitized byanalog-to-digital converter 775 (ADC). The analog-to-digital converter775 supplies the digitized pixel signals to an image processor 780 whichforms a digital image. The image processor 780 may also determine thegain setting of the imager 700, which can be used to set the level ofthe voltage applied to the pixels transfer gates (as described abovewith respect to FIG. 7).

FIG. 10 shows a system 1000, a typical processor system modified toinclude an imaging device 1008 (such as the imaging device 700illustrated in FIG. 9) of the invention. The processor system 1000 isexemplary of a system having digital circuits that could include imagesensor devices. Without being limiting, such a system could include acomputer system, camera system, scanner, machine vision, vehiclenavigation, video phone, surveillance system, auto focus system, startracker system, motion detection system, image stabilization system, anddata compression system, and other systems employing an imager.

System 1000, for example a camera system, generally comprises a centralprocessing unit (CPU) 1002, such as a microprocessor, that communicateswith an input/output (I/O) device 1006 over a bus 1020. Imaging device1008 also communicate's with the CPU 1002 over the bus 1020. Theprocessor-based system 1000 also includes random access memory (RAM)1004, and can include removable memory 1014, such as flash memory, whichalso communicate with the CPU 1002 over the bus 1020. The imaging device1008 may be combined with a processor, such as a CPU, digital signalprocessor, or microprocessor, with or without memory storage on a singleintegrated circuit or on a different chip than the processor.

It should be noted that the invention has been described with referenceto photodiode photosensors, but it should be appreciated that theinvention may be utilized with any type of photosensor used in animaging pixel circuit such as, but not limited to, photogates,photoconductors, photodiodes and pinned photodiodes and variousconfigurations of photodiodes and pinned photodiodes.

It should also be appreciated that the small voltage does not need to beapplied during the entire acquisition period. That is, the small voltagemay be applied for only a portion of the charge acquisition period. Itshould also be appreciated that the imager of the invention could bedesigned to include all of the embodiments of the invention with a userselectable or application specific selectable option to determine whichembodiment is performed during the operation of imager. For example, ahardware register could be used and set to indicate that the FIG. 2 a or3 a timing should be used or that method 600 should be used during theoperation of the imager.

The processes and devices described above illustrate preferred methodsand typical devices of many that could be used and produced. The abovedescription and drawings illustrate embodiments, which achieve theobjects, features, and advantages of the present invention. However, itis not intended that the present invention be strictly limited to theabove-described and illustrated embodiments. Any modification, thoughpresently unforeseeable, of the present invention that comes within thespirit and scope of the following claims should be considered part ofthe present invention.

1. A method of operating an imager pixel circuit comprising aphotosensor, transfer gate and a floating diffusion region, said methodcomprising the act of: applying a non-zero positive voltage to thetransfer gate during a charge acquisition period for the photosensor. 2.The method of claim 1, wherein the voltage is applied to the transfergate for the entirety of the acquisition period.
 3. The method of claim1, wherein the voltage is applied to the transfer gate for a portion ofthe acquisition period.
 4. The method of claim 1, further comprising theact of determining a gain setting of the pixel circuit, wherein a levelof the applied voltage is based on the gain setting.
 5. A method ofoperating an imager pixel circuit comprising a photosensor, a transfergate and a floating diffusion region, said method comprising the actsof: initiating a charge acquisition period for the photosensor; andcreating a depletion region underneath the transfer gate during theacquisition period by applying a positive voltage to the transfer gate,wherein the depletion region serves as a path for dark current electronsto flow to the floating diffusion region.
 6. The method of claim 5,wherein said positive voltage is applied during the entirety of theacquisition period.
 7. The method of claim 5, wherein said positivevoltage is applied during a portion of the acquisition period.
 8. Themethod of claim 5, wherein a level of the positive voltage is dependentof a gain setting of the pixel circuit.
 9. A method of operating animager pixel circuit comprising a photosensor, a transfer gate and afloating diffusion region, said method comprising the acts of:initiating a charge acquisition period for the photosensor; andcombining dark electrons underneath the transfer gate with electronholes to substantially reduce a number of dark current electrons byapplying a positive voltage to the transfer gate during the chargeacquisition period.
 10. The method of claim 9, wherein the voltage isapplied during the entirety of the acquisition period.
 11. The method ofclaim 9, wherein the voltage is applied during a portion of theacquisition period.
 12. An imager comprising: an array of pixels, eachpixel comprising a photosensor, transfer gate and a floating diffusionregion; and a control circuit electrically connected to said array, saidcontrol circuit configured to operate each pixel in a selected row byinitiating a charge acquisition period for the photosensor, andconfigured to apply a positive voltage to the transfer gate of eachpixel in the selected row during the acquisition period.
 13. The imagerof claim 12, wherein the voltage is applied to the transfer gate for theentirety of the acquisition period.
 14. The imager of claim 12, whereinthe voltage is applied to the transfer gate for a portion of theacquisition period.
 15. The imager of claim 12, wherein the positivevoltage is greater than approximately 0.0 volts, but no more thanapproximately 0.8 volts.
 16. The imager of claim 12, wherein saidcontrol circuit further controls the pixel by resetting the floatingdiffusion region after the acquisition period.
 17. The imager of claim12, wherein a level of the positive voltage is based on a gain settingof the imager.
 18. The imager of claim 12, wherein said imager is partof an image processing system.
 19. The imager of claim 21, wherein saidimager is part of a camera system.
 20. An imager comprising: an array ofpixels, each pixel comprising a photosensor, a transfer gate and afloating diffusion region; and a control circuit electrically connectedto said array, said control circuit configured to operate each pixel ina selected row by initiating a charge acquisition period for thephotosensor, and applying a positive voltage to the transfer gate ofeach pixel in the selected row during the acquisition period, wherein alevel of the voltage is based on a gain setting of the imager.
 21. Theimager of claim 20, further comprising means for determining the gainsetting of the imager.
 22. The imager of claim 20, wherein if the gainsetting is below a predefined threshold, the control circuit isconfigured to apply a ground potential to the transfer gate during theacquisition period.
 23. The imager of claim 20, wherein said imager ispart of an image processing system.
 24. The imager of claim 20, whereinsaid imager is part of a camera system.
 25. An active pixel comprising:a light sensing element formed in a semiconductor substrate; and atransfer transistor formed between said light sensing element and afloating node and selectively operative to transfer a signal from saidlight sensing element to said floating node, wherein said transfertransistor is positively biased during an integration period during afirst mode of operation.
 26. The pixel of claim 25, wherein said lightsensing element is selected from the group of photodiode, pinnedphotodiode, partially pinned photodiode, or photogate.
 27. The pixel ofclaim 25, wherein said transfer transistor is turned off during saidintegration period during a second mode of operation.
 28. The pixel ofclaim 25, wherein said first mode of operation is used if a level ofincident light is low.
 29. The pixel of claim 27, wherein said secondmode of operation is used if a level of incident light is normal. 30.The pixel of claim 25, further including an amplification transistorcontrolled by said floating node, wherein said amplification transistoroutputs an amplified version of said signal to a column bitline.
 31. Thepixel of claim 25, further including a reset transistor operative toreset said floating node to a reference voltage.
 32. The pixel of claim25, wherein said transfer transistor is positively biased such that itis partially turned on during said integration period.
 33. The pixel ofclaim 25 wherein said pixel is integrated into a CMOS image sensor. 34.The pixel of claim 25 wherein said pixel is part of a 4T, 5T, 6T, or 7Tpixel architecture.
 35. A method of operating a pixel of an imagesensor, said pixel including a light sensing element, a transfertransistor between said light sensing element and a floating node fortransferring a signal from said light sensing element to said floatingnode, and an amplification transistor modulated by said signal on saidfloating node, the method comprising: determining a level of incidentlight; if said level of illumination is low: partially turning on saidtransfer transistor during an integration period; and if said level ofillumination is normal: substantially turning off said transfertransistor during said integration period.
 36. The method of claim 35wherein said light sensing element is selected from the group ofphotodiode, pinned photodiode, partially pinned photodiode, orphotogate.
 37. The method of claim 35 wherein said amplificationtransistor outputs an amplified version of said signal to a columnbitline.
 38. The method of claim 35 wherein said pixel further includesa reset transistor operative to reset said floating node to a referencevoltage.
 39. An active pixel comprising: a light sensing element formedin a semiconductor substrate; and a transfer transistor formed betweensaid light sensing element and a floating node and selectively operativeto transfer a signal from said light sensing element to said floatingnode, wherein said transfer transistor is positively biased such thatsaid transfer transistor is partially turned on during an integrationperiod and substantially fully turned on during a readout period duringa first mode of operation.
 40. The pixel of claim 39, wherein said lightsensing element is selected from the group of photodiode, pinnedphotodiode, partially pinned photodiode, or photogate.
 41. The pixel ofclaim 39, wherein said transfer transistor is turned off during saidintegration period during a second mode of operation.
 42. The pixel ofclaim 39, wherein said first mode of operation is used if a level ofincident light is low.
 43. The pixel of claim 41, wherein said secondmode of operation is used if a level of incident light is normal. 44.The pixel of claim 39 further including an amplification transistorcontrolled by said floating node, wherein said amplification transistoroutputs an amplified version of said signal to a column bitline.
 45. Thepixel of claim 39 further including a reset transistor operative toreset said floating node to a reference voltage.
 46. The pixel of claim39 wherein said transfer transistor is positively biased such that it ispartially turned on during said integration period.
 47. The pixel ofclaim 39 wherein said pixel is integrated into a CMOS image sensor. 48.The pixel of claim 39 wherein said pixel is part of a 4T, 5T, 6T, or 7Tpixel architecture.